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INTEGRATED CIRCUITS
DATA SHEET
TDA4882 Advanced monitor video controller for OSD
Product specification Supersedes data of December 1994 File under Integrated Circuits, IC02 1997 Sep 04
Philips Semiconductors
Product specification
Advanced monitor video controller for OSD
CONTENTS 1 2 3 4 5 6 7 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 8 9 10 11 11.1 12 13 14 14.1 14.2 14.3 15 16 FEATURES GENERAL DESCRIPTION QUICK REFERENCE DATA ORDERING INFORMATION BLOCK DIAGRAM PINNING FUNCTIONAL DESCRIPTION General Brightness control Contrast control Output stages Input clamping Vertical blanking Horizontal blanking Cut-off and black-level stabilization On Screen Display Test mode LIMITING VALUES THERMAL CHARACTERISTICS CHARACTERISTICS APPLICATION AND TEST INFORMATION Recommendations for building the application board INTERNAL PIN CONFIGURATION PACKAGE OUTLINE SOLDERING Introduction Soldering by dipping or by wave Repairing soldered joints DEFINITIONS LIFE SUPPORT APPLICATIONS
TDA4882
1997 Sep 04
2
Philips Semiconductors
Product specification
Advanced monitor video controller for OSD
1 FEATURES 2 GENERAL DESCRIPTION
TDA4882
* 85 MHz video controller * Fully DC controllable * 3 separate video channels * Input black-level clamping * White level adjustment for 2 channels only * Brightness control with correct grey scale tracking * Contrast control for all 3 channels simultaneously * Cathode feedback to internal reference for cut-off control, which allows unstabilized video supply voltage * Current outputs for RGB signal currents * RGB voltage outputs to external peaking circuits * Blanking and switch-off input for screen protection * Sync on green operation possible * On Screen Display (OSD) facility. 3 QUICK REFERENCE DATA SYMBOL VP IP Vi(b-w) Vo(b-w) PARAMETER positive supply voltage supply current input voltage, black-to-white output voltage, black-to-white
The TDA4882 is an RGB pre-amplifier for colour monitor systems with SVGA performance, intended for DC or AC coupling of the colour signals to the cathodes of the CRT. With special advantages the circuit can be used in conjunction with the TDA485x monitor deflection IC family.
CONDITIONS
MIN. 7.2 36 -
TYP. 8.0 48 0.7 0.79
MAX. 8.8 60 1.0 -
UNIT V mA V V
nominal contrast; channels 1 and 3 gain control pins open-circuit
-
Io(b-w) IOM B Gnom
output current, black-to-white peak output current bandwidth nominal voltage gain -3 dB nominal contrast; channels 1 and 3 gain control pins open-circuit relative to Gnom Vi(CC) = 1 to 6 V Vi(CC) = 0.7 V
- - 70 -
50 - 85 1
- 100 - -
mA mA MHz dB
G CRcontrast COSD(min) Vbl Tamb 4
gain control difference for 2 channels contrast control minimum contrast for OSD brightness control related to nominal output signal amplitude operating ambient temperature
-5 -22 - -11 -20
- - -40 - -
+2.6 +3.4 - +34 +70
dB dB dB % C
ORDERING INFORMATION TYPE NUMBER PACKAGE NAME DIP20 DESCRIPTION plastic dual in-line package; 20 leads (300 mil) VERSION SOT146-1
TDA4882
1997 Sep 04
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Philips Semiconductors
Product specification
Advanced monitor video controller for OSD
5 BLOCK DIAGRAM
TDA4882
handbook, full pagewidth
VP = 8 V VP 10 k brightness control signal input 75 22 nF 1 VOLTAGE CONVERTER
6.2 V
TDA4882
20 2 CLAMP CLIPPING BAV21 voltage output 33 33 BFQ235 8V 10 k cut-off control 220 current output 1.5 k VCRT = 90 V
10 M 19
VP 10 k gain control 3 VOLTAGE CONVERTER 18 feedback
68 k
CHANNEL 1
15 k 6.8 k
4 1.5 k current 17 output 22 nF 5 CLAMP CLIPPING voltage 16 output 33 REF GAIN BFQ256 VP 10 k 6 contrast control VOLTAGE CONVERTER CHANNEL 2 15 feedback 33 10 k 15 k 6.8 k cut-off control 60 MHz VCRT = 90 V BFQ236 BAV21 10 1 k BFQ235 10 68 k 8V 220 25 MHz
signal input 75
10 M
40 MHz CRT
VP
7
+
current 14 output
860
VCRT = 65 V
signal input 75
22 nF
BFQ236 BAV21 10
8
CLAMP CLIPPING voltage 13 output 18
10 M BFQ235
1 k 10
47 nF
100
18
VCRT 9 horizontal blanking switch off VOLTAGE CONVERTER input clamping BFQ256 CHANNEL 3 test mode ultra black blanking 10 clamping pulse vertical blanking test mode PULSE DECODER output clamping 5.8 V 11 10 k gain control VP horizontal blanking 12 feedback 10 k 93 k 10 k cut-off control
MED910
Fig.1 Block diagram and basic application circuits for DC and AC coupling.
1997 Sep 04
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Philips Semiconductors
Product specification
Advanced monitor video controller for OSD
6 PINNING SYMBOL BC VIN1 GC1 GND VIN2 CC VP VIN3 HBL CL GC3 FB3 VOUT3 IOUT3 FB2 VOUT2 IOUT2 FB1 VOUT1 IOUT1 7 7.1 PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 DESCRIPTION brightness control signal input channel 1 gain control channel 1 ground signal input channel 2 contrast control, OSD switch supply voltage signal input channel 3 horizontal blanking, switch-off input clamping, vertical blanking, test mode gain control channel 3 feedback channel 3 voltage output channel 3 current output channel 3 feedback channel 2 voltage output channel 2 current output channel 2 feedback channel 1 voltage output channel 1 current output channel 1 Fig.2 Pin configuration.
VIN2 5
handbook, halfpage
TDA4882
BC 1 VIN1 2 GC1 3 GND 4
20 IOUT1 19 VOUT1 18 FB1 17 IOUT2 16 VOUT2
TDA4882
CC 6 VP 7 VIN3 8 HBL 9 CL 10
MHA815
15 FB2 14 IOUT3 13 VOUT3 12 FB3 11 GC3
FUNCTIONAL DESCRIPTION General
For nominal brightness (pin 1 open-circuit) the signal black level is equal to the reference black level. 7.3 Contrast control
Figure 4 illustrates the signal processing. The RGB input signals 0.7 V (p-p) are capacitively coupled into the TDA4882 from a low ohmic source and are clamped to an internal DC voltage (artificial black level). Composite signals will not disturb normal operations because an internal clipping circuit cuts all signal parts below black level. Channels 1 and 3 have a maximum total voltage gain of 7 dB (maximum contrast and maximum individual channel gain), channel 2 having 4.4 dB (maximum contrast and nominal gain). With the nominal channel gain of 1 dB and nominal contrast setting the nominal black-to-white output signal is 0.79 V (p-p). Brightness, contrast and gain control is by DC voltage. 7.2 Brightness control
Contrast is voltage controlled to affect the three channels simultaneously (Fig.4). To provide the correct white point, individual gain controls adjust the signals of channels 1 and 3 relative to the reference channel 2. Gain setting also changes contrast to achieve correct grey scale tracking. 7.4 Output stages
Brightness control (Fig.4) yields a simultaneous signal black-level shift of the three channels relative to a reference black level.
The output stages provide both voltage and current outputs. External cascode transistors reduce power consumption of the IC and prevent breakdown of the output transistors. Signal output currents and peaking characteristics are determined by external components at the voltage outputs and the video supply. The channels have separate internal feedback loops which ensure large signal linearity and marginal signal distortion irrespective of output transistor thermal VBE variation (Fig.8).
1997 Sep 04
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Philips Semiconductors
Product specification
Advanced monitor video controller for OSD
7.5 Input clamping
TDA4882
The clamping pulse (Fig.17) is for input clamping only. The input signals are at black level during the clamping pulse and are clamped to an internal artificial black level. The coupling capacitors provide black-level storage. The threshold for the clamping pulse is higher than that for vertical blanking, therefore, the rise and fall times of the clamping pulse need to be faster than 75 ns/V during transition from 1 to 3.5 V. 7.6 Vertical blanking
Ultra-black level is the lowest possible channel output voltage and is not dependent on cut-off stabilization. 7.8 Cut-off and black-level stabilization
The vertical blanking pulse (Fig.17) will be detected if the input voltage is higher than the threshold voltage for approximately 320 ns but does not exceed the threshold for the clamping pulse in the time between. During the vertical blanking pulse the input clamping is disabled to avoid misclamping in the event of composite input signals. The input signal is blanked and the artificial black level is inserted instead. Also the brightness is set internally to its nominal value, thus the output signal is at reference black level. The DC value of the reference black level will be adjusted by cut-off stabilization. 7.7 Horizontal blanking
For cut-off stabilization (DC coupling to the CRT) and black-level stabilization (AC coupling) the video signal at the cathode or the coupling capacitor is divided by an adjustable voltage divider and fed to the channel feedback inputs. During horizontal blanking time this signal is compared with an internal DC voltage of approximately 5.8 V. Any difference will lead to a reference black-level correction by charging or discharging the integrated capacitor which stores the reference black-level information between the horizontal blanking pulses. 7.9 On Screen Display
For OSD (Fig.3), fast switching of control pin 6 to less than 1 V (e.g. 0.7 V) blanks the input signals. The OSD signals can easily be inserted to the external cascode transistor. 7.10 Test mode
During horizontal blanking (Fig.18) the output signal is set to reference black level and output clamping is activated. If the voltage exceeds the switch-off threshold, the signal is blanked and switched to ultra-black level for screen protection and spot suppression during V-flyback.
During test mode (pins 9 and 10 connected to VP) the black levels at the channel voltage outputs are set internally to typical 0.7 V with nominal brightness and 3 V DC at channel signal inputs.
handbook, full pagewidth
20
channel 1
17
channel 2
TDA4882
contrast BFQ235 6 14 100 pF OSD fast blanking 1 k 4.7 k PH2222 150 depending on channel gain 1 k to 10 k
MHA816
current output PH2222
channel 3 220 OSD signal input
Fig.3 OSD application.
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Philips Semiconductors
Product specification
Advanced monitor video controller for OSD
8 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL Vext pin 7 (VP) pins 2, 5 and 8 (signal inputs) pins 20, 17 and 14 (current outputs) pins 12, 15 and 18 (channel feedback inputs) pins 1, 6, 3 and 11 (brightness, contrast and gain control inputs) pin 9 (horizontal blanking input) pin 10 (input clamping input) Io(av) IOM Ptot Tstg Tamb Tj VESD Notes average output current (pins 20, 17 and 14); note 1 peak output current (pins 20, 17 and 14) total power dissipation storage temperature operating ambient temperature junction temperature electrostatic handling for all pins; note 2 PARAMETER external DC voltage applied to the following pins: 0 -0.1 -0.1 -0.1 -0.1 -0.1 -0.1 0 0 - -25 -20 -25 -500 8.8 VP VP +0.7 VP MIN.
TDA4882
MAX. V V V V V V V
UNIT
VP + 0.7 VP + 0.7 50 100 1200 +150 +70 +150 +500
mA mA mW C C C V
1. Signal amplitude of 50 mA black-to-white is possible if the average current (including blanking times and signal variation against time) does not exceed 50 mA. The maximum power dissipation of 1200 mW has to be considered. 2. Equivalent to discharging a 200 pF capacitor through a 0 series resistor. 9 THERMAL CHARACTERISTICS SYMBOL Rth(j-a) PARAMETER thermal resistance from junction to ambient CONDITIONS in free air VALUE 65 UNIT K/W
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Philips Semiconductors
Product specification
Advanced monitor video controller for OSD
TDA4882
10 CHARACTERISTICS VP = 8.0 V; Tamb = 25 C; all voltages measured to GND (pin 4); note 1; see Fig.4; unless otherwise specified. SYMBOL VP IP Vi(b-w) VI(clamp) II PARAMETER supply voltage supply current CONDITIONS MIN. 7.2 36 - 2.8 no clamping; Vi = VI(clamp); Tamb = -20 to +70 C during clamping; Vi = VI(clamp) + 0.7 V during clamping; Vi = VI(clamp) - 0.7 V Brightness control; note 2; Fig.5 Vi(BC) Ri(BC) Vi(BC)(nom) Vbl input voltage input resistance input voltage for nominal brightness pin 1 open-circuit black-level voltage change at Vi(BC) = 1.0 V voltage outputs referred to Vi(BC) = 6.0 V reference black level during output pin 1 open-circuit clamping (Vi(HBL) > 1.6 V) related to output signal amplitude with nominal 0.7 V (p-p) input signal and nominal contrast (Vi(CC) = 4.3 V) for any gain setting difference of Vbl between any two channels 1.0 40 2.0 -13 30 - - 50 2.25 -11 34 - 6.0 60 2.5 -9.5 37 0.8 V k V % % % -0.05 50 -120 TYP. 8.0 48 MAX. 8.8 60 UNIT V mA
Video signal inputs (channels 1, 2 and 3) input voltage, black-to-white DC voltage during input clamping (artificial black + VBE) DC input current 0.7 3.1 +0.05 75 -75 1.0 3.4 +0.25 0 120 -50 V V A A A
VBT
-1.2
0
+1.2
%
Contrast control; note 3; Fig.6 Vi(CC) Vi(CC)(max) Vi(CC)(nom) Ii(CC) C/Cnom input voltage maximum input voltage input voltage for nominal contrast input current note 4 Vi(CC) = 4.3 V 1.0 - - -5 2.4 -26 - - - - - 4.3 -1 3.4 -22 0.7 0 7 6.0 - -0.1 - -19 - 0.5 20 V V A dB dB V dB ns VP - 1 V
contrast relative to nominal contrast Vi(CC) = 6.0 V; pins 3 and 11 open-circuit Vi(CC) = 1.0 V; pins 3 and 11 open-circuit
Vi(CC)(min) Gtrack tdf(C)
input voltage for minimum contrast tracking of output signals of channels 1, 2 and 3 delay between leading (falling) edges of contrast voltage and voltage output waveforms
pins 3 and 11 open-circuit 1 V < Vi(CC) < 6 V; note 5 Vi(CC) = 4.3 V to 0.7 V; input fall time at pin 6: tf(CC) = 2 ns; note 6; Fig.10
1997 Sep 04
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Philips Semiconductors
Product specification
Advanced monitor video controller for OSD
TDA4882
SYMBOL tdr(C)
PARAMETER delay between trailing edges (rising) of contrast voltage and voltage output waveforms
CONDITIONS Vi(CC) = 0.7 V to 4.3 V; input rise time at pin 6: tr(CC) = 2 ns; note 6; Fig.10
MIN. -
TYP. 15
MAX. 25
UNIT ns
tf(C)
fall time of voltage output waveform 90% to 10% amplitude; input fall time at pin 6: tf(CC) = 2 ns; note 6; Fig.10 rise time of voltage output waveform 10% to 90% amplitude; input rise time at pin 6: tr(CC) = 2 ns; note 6; Fig.10
-
6
15
ns
tr(C)
-
6
15
ns
Gain control (channel 1 and channel 3); note 7; Fig.7 Vi(GC) Vi(GC)(nom) Ri(GC) G input voltage input voltage for nominal gain input resistance gain control difference relative to nominal gain (channels 1 and 3 only) Vi(CC) = 4.3 V; Vi(GC) = 6 V Vi(CC) = 4.3 V; Vi(GC) = 1 V pins 3 and 11 open-circuit 1.0 3.6 44 2 -5.5 - 3.75 55 2.6 -5 6.0 3.95 66 3.3 -4.5 V V k dB dB
Feedback input (channels 1, 2 and 3); note 8; Fig.8 Vref(int) Io(FB)(max) Vbl(CRT) Vref(T) Vref(int)(VP) internal reference voltage maximum output current black-level variation at CRT variation of Vref(int) in the temperature range variation of Vref(int) with supply voltage during output clamping; Vi(FB) = 3 V note 9 Tamb = -20 to +70 C 7.2 V VP 8.8 V 5.6 -500 0 0 0 5.8 -100 40 20 60 6.1 -60 200 50 100 V nA mV mV mV
Voltage outputs (channels 1, 2 and 3) Vo(b-w)(nom) Vblx(max) Vbl(SO) nominal signal output voltage (black-to-white value) maximum adjustable black-level voltage black-level voltage during switch-off, equal to minimum adjustable black-level voltage black-level voltage during test mode signal-to-noise ratio output thermal distortion black-level variation between clamping pulses maximum offset during sync clipping pins 3 and 11 open-circuit; Vi(CC) = 4.3 V; Vi(b-w) = 0.7 V during output clamping; Tamb = -20 to +70 C Vi(HBL) = VP; RO = 33 ; Tamb = -20 to +70 C Vi(HBL) = VP; Vi(CL) = VP; pin 1 open-circuit; Vi = VI(clamp); note 10 note 11 Io(b-w) = 50 mA; note 12 line frequency 30 kHz VI < VI(clamp); note 13; Fig.9 0.69 1 30 0.79 1.2 45 0.89 1.4 100 V V mV
Vbl(TST)
0.3
0.7
1.2
V
S/N dO(th) Vbl(fl) Voffset(max)
- - - 0
50 0.6 0.5 7
44 1 4.5 15
dB % mV mV
1997 Sep 04
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Philips Semiconductors
Product specification
Advanced monitor video controller for OSD
TDA4882
SYMBOL Vo(b-w)(T)
PARAMETER variation of nominal output signal (black-to-white value) with temperature
CONDITIONS pins 3 and 11 open-circuit; Vi(CC) = 4.3 V; Vi(b-w) = 0.7 V; Tamb = -20 to +70 C
MIN. 0
TYP. 2.5
MAX. 10
UNIT %
Current outputs (channels 1, 2 and 3); note 14 Io(b-w) output current (black-to-white value) - with peaking Io = 50 mA Io = 100 mA Vi(HBL) = VP; RO = 33 70 MHz; single channel 10% to 90% amplitude; input rise time = 1 ns single channel; input rise time = 2.5 ns; Vi(b-w) = 0.7 V; pins 3 and 11 open-circuit; Vi(CC) = 4.3 V - - - 0 - - - 50 - - - 20 - 100 2.0 2.2 900 mA mA V V A
V20-19; V17-16; start of HF-saturation voltage of V14-13 output transistors Ibl(SO) G(f) tr(O) dVO output current during switch-off
Frequency response at voltage outputs; note 15; Figs 11, 12 and 13 gain decrease by frequency response rise time at voltage output overshoot of output signal pulse related to actual output pulse amplitude 1.3 4.1 4 3 5.0 8 dB ns %
Crosstalk at voltage outputs with speed up circuit; note 16; Figs 14, 15 and 16 ct(tr) Vi(HBL) transient crosstalk - - -20 dB
Threshold voltages for clamping, blanking and switch-off; note 17 threshold for horizontal blanking (blanking, output clamping) threshold for switch-off (blanking, minimum black-level, no output clamping) Ri(HBL) td(Hblank) input resistance delay between horizontal blanking input and output signal blanking threshold for vertical blanking (blanking, no input clamping) threshold for clamping (input clamping, no blanking) threshold for test mode (no clamping, no blanking, see Vbl(TST) above) Ii(CL) current against ground input rise time at pin 9 > 100 ns; note 18; Fig.18 note 19; Fig.17 note 19; Fig.17 for test mode also Vi(HBL) > 6.8 V (switch-off) Vi(CL) < VP - 1 V Vi(CL) VP - 1 V 1.2 5.8 1.4 6.5 1.6 6.8 V V
50 -
80 40
110 60
k ns
Vi(CL)
1.2 2.6
1.4 3.0
1.6 3.5 VP
V V V
VP - 1 -
-3 -
-1 100
- -
A A
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Philips Semiconductors
Product specification
Advanced monitor video controller for OSD
TDA4882
SYMBOL tr(CL), tf(CL) tw(clamp) td(Vblank)
PARAMETER width of clamping pulse delay between vertical blanking input and internal blanking
CONDITIONS
MIN. - 0.6 260
TYP. - - 320
MAX. 75 - 380
UNIT ns/V s ns
rise and fall time for clamping pulse note 19; Fig.17 note 19; Fig.17
Notes to the characteristics 1. Definition of levels: a) Artificial black level: internal signal level behind input emitter follower during input clamping and signal clipping. This level is inserted instead of the input signal during blanking. b) Reference black level: DC voltage during output clamping at voltage outputs, not influenced by brightness, contrast or gain setting, adjustable by cut-off stabilization. c) Cut-off level: corresponding DC voltage at CRT cathode in closed feedback loop. d) Black level: actual signal black level at either the voltage outputs or cathode, it can be adjusted by (brightness x gain), it refers to reference black level or cut-off level. e) Ultra-black level, switch-off level: lowest adjustable reference black level, lowest signal level at voltage outputs. f) The minimum guaranteed control range for reference black level is 0.1 to 1 V. The ultra-black level is dependent on the external resistor RO at pins 13, 16 and 19 (voltage outputs) to ground. Ro g) V bl(SO) ------------------------------ x 4.65 V 3.5 k + R o 2. Linear control range is 1 to 6 V for Vi(BC), independent of supply voltage. 3. Linear control range is 1 to 6 V for Vi(CC), independent of supply voltage. Open pin 6 leads to maximum contrast setting. It is recommended not to exceed Vi(CC) = VP - 1 V to avoid saturation of internal circuitry. For Vi(CC) < Vi(CC)(min) 0.7 V a small negative signal ( -40 dB) will appear. For frequency dependency of contrast control see note 15. 4. Definition for nominal output signals: input Vi(b-w) = 0.7 V, gain pins 3 and 11 open-circuit, contrast control Vi(CC) = Vi(CC)(nom). 5. A 1 A 20 A 1 A 30 A 2 A 30 G track = 20 x maximum of log -------- x -------- ; log -------- x -------- ; log -------- x -------- dB A 10 A 2 A 10 A 3 A 20 A 3 Ax: signal output amplitude in channel x at any contrast setting between 1 and 6 V. Ax0: signal output amplitude in channel x at nominal contrast and same gain setting. 6. Typical step in contrast voltage and response at signal outputs for nominal input signal Vi(b-w) = 0.7 V (OSD fast blanking input/output). 7. Linear control range is 1 to 6 V for Vi(GC), independent of supply voltage. 8. The internal reference voltage can be measured at pins 18, 15 and 12 (channel feedback inputs) during output clamping (Vi(HBL) = 2 V) in closed feedback loop. 9. Slow variations of video supply voltage VCRT (Fig.1) will be suppressed at CRT cathode by cut-off stabilization. Change of VCRT by 5 V leads to specified change of cut-off voltage. 10. The test mode allows testing without input and output clamping pulses. The signal inputs have to be biased via resistors to the previously measured clamp voltages of approximately 3 V (artificial black level + VBE). Signal and brightness blanking is not possible during test mode. The current outputs should be adjusted by resistors >> R0 from voltage outputs to a positive voltage (e.g. VP).
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Philips Semiconductors
Product specification
Advanced monitor video controller for OSD
11. The signal-to-noise ratio is calculated by the formula (frequency range 1 to 70 MHz): peak-to-peak value of the nominal signal output voltage S --- = 20 x log -------------------------------------------------------------------------------------------------------------------------------------------------- dB RMS value of the noise output voltage N
TDA4882
12. Large output swing e.g. Io(b-w) = 50 mA leads to signal-dependent power dissipation in output transistors. Thermal VBE variation is compensated. 13. Composite signals will not disturb normal operation because an internal clipping circuit cuts all signal parts below black level. 1 1 14. The output current approximately follows the equation I o = V o ------- + ----------------- - 500 A for Vo > Vbl(SO) and with R O 2.2 k RO = external resistor at voltage output to ground. The external RC combination (Fig.1) at pins 19, 16 and 13 (voltage outputs) enables peak currents during transients. 15. Frequency response, crosstalk and pulse response have been measured at voltage outputs on a special printed-circuit board with 50 line in/out connections and without peaking, see Chapter 11. 16. Crosstalk between any two voltage outputs (e.g. channels 1 and 2). a) Input conditions: one channel (channel 1) with nominal input signal and minimum rise time. The inputs of the other channels capacitively coupled to ground (channels 2 and 3). Gain pins 3 and 11 open-circuit. b) Output conditions: output signal of channel 1 is set by contrast control voltage, to Vo(b-w) = Vo(VOUT1) = 0.7 V, the rise time should be 5 ns. Output signal of channel 2 then is Vo(b-w) = Vo(VOUT2). V o(VOUT2) c) Transient crosstalk: ct(tr) = 20 x log ----------------------- dB V o(VOUT1) d) Crosstalk as a function of frequency has been measured without peaking circuit, with nominal input signal and nominal settings. 17. The internal threshold voltages are derived from a stabilized voltage. The internal pulses are generated while the input pulses are higher than the thresholds. Voltages less than -0.1 V at pins 9 and 10 can influence black-level control and should be avoided. 18. The delay between HBL input pulse (horizontal blanking) and output signal blanking pulse and also brightness blanking (Vbl), at the voltage outputs, depends on the input rise time of the HBL pulse. The specified values for td(Hblank) are valid for HBL rise times greater than 100 ns only. 19. For 75 ns/V < tr(CL), tf(CL) < 240 ns/V, generation of internal input clamping and blanking pulse is not defined. Pulses not exceeding the threshold of input clamping (typical 3 V) will be detected as blanking pulses.
1997 Sep 04
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Philips Semiconductors
Product specification
Advanced monitor video controller for OSD
TDA4882
input handbook, full pagewidth signals input signal at pins 2, 5 and 8 with sync (on green)
video signal black level equal to artificial black level + VBE by input clamping (approximately 3 V)
input clamping pulse at pin 10 horizontal blanking and output clamping pulse at pin 9
video portion
horizontal flyback and output clamping black level equal to artificial black level by input clamping and storage by coupling capacitor inserted artificial black level max. nom. min. black level due to brightness setting reference black level brightness is set to nominal value during horizontal blanking max. nom.
internal signal behind input stage sync clipping to artificial black level output signals (pins 19, 16 and 13) at nominal gain and contrast setting and maximum/nominal/ minimum brightness setting
at nominal gain and maximum brightness setting and maximum/nominal/ minimum contrast setting
min.
black level for maximum brightness reference black level
max. at nominal contrast and maximum brightness setting and maximum/nominal/ minimum gain setting nom. min.
grey scale
reference black level ultra black level ground signal at CRT cathode high tension supply voltage (e.g. 90 V) (raster) cut-off level black level at nominal gain and contrast setting and maximum brightness setting
grey scale
MHA817
Fig.4 Signal processing.
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Philips Semiconductors
Product specification
Advanced monitor video controller for OSD
TDA4882
handbook, halfpage
50 40 30
MHA818
400 (mV)
handbook, halfpage
1400
MHA819
Vbl (%)
300
signal amplitude (mV) 1000
4 3 2
(dB)
200 20 10 0 -10 -20 -200 -30 0 2 2.24 4 6 Vi (BC) 8 -200 0 0.7 2 4 4.3 6 Vi(CC) (V) 8 100 800 600 400 200 0
1 0 -1 -3 -5 -10 -20 -40
0 -100
Fig.5 Typical brightness characteristic.
Fig.6 Typical contrast characteristic.
handbook, halfpage
1200
MHA821
3 (dB) 2 1 0 -1 -2 -3 -4 -5 -6 -8
handbook, halfpage
5.85
MHA822
signal amplitude (mV) 800
5.84 Vref(int) (V) 5.83 5.82 5.81 5.80 5.79 5.78
VP = 8.8 V
8.0 V
400
7.2 V 5.77 5.76
0 0 2 4 3.75 6 Vi(GC) (V) 8
5.75 -20
0
20
40
60
80 100 Tamb (C)
Conditions: 0.5 V reference black level, no signal.
Fig.8 Fig.7 Typical gain characteristic.
Typical variation of Vref(int) with temperature and supply voltage.
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Philips Semiconductors
Product specification
Advanced monitor video controller for OSD
TDA4882
handbook, full pagewidth
input signal
output signal
Voffset(max)
MHA823
Fig.9 Typical sync clipping.
handbook, full pagewidth
OSD pulse at pin 6 (V) 4.3
tf(CC)
tr(CC) 90% 50%
0.7 t output signal at pins 19, 16 and 13 (V) Vbl + Vo(b-w) = 1.5 Vo(b-w) Vbl = 0.7 t tf(C) tr(C) tdf(C) tdr(C)
10%
90% 50% 10%
MHA820
Fig.10 Typical OSD fast blanking input/output waveforms.
1997 Sep 04
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Philips Semiconductors
Product specification
Advanced monitor video controller for OSD
TDA4882
handbook, full pagewidth
800 input pulse (mV) 600 90%
MHA825
400 tr 2.5 ns 200 10% 0 tf 2.5 ns
1000 output pulse (mV) 800 90% 600
400 tr 4.4 ns 200 10% 0 tf 4.8 ns
-200
0
20
40
60
80
t (ns)
100
Solid line: single channel. Dotted line: white pattern.
Fig.11 Typical pulse response: VIN1, VIN2 and VIN3 VOUT1, VOUT2 and VOUT3.
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Philips Semiconductors
Product specification
Advanced monitor video controller for OSD
TDA4882
handbook, full pagewidth
3
MHA824
signal (dB) 0
-3
-6
-9
-12
-15
1
10
102
f (MHz)
103
Solid line: single channel. Dotted line: white signal.
Fig.12 Typical frequency response.
handbook, full pagewidth
10
MHA826
signal (dB) 0
Vi(cc) = 7V 6V 5V 4V 3V
-10
2V
-20 1V
Vi(cc) = 0.7 V
-30
Vi(cc) = 0.7 V 1 10 70 102 120 f (MHz) 103
Solid line: single channel. Dotted line: white signal.
Fig.13 Typical characteristic of contrast control as a function of frequency.
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Philips Semiconductors
Product specification
Advanced monitor video controller for OSD
TDA4882
MHA827
handbook, full pagewidth
0 signal (dB) -10 channel(1) 1
-20 2 3 -30
-40 102 103
1 (1) Solid line: channel 1. Dashed line: channel 2. Dotted line: channel 3.
10
f (MHz)
Fig.14 Typical crosstalk: channel 1 2 and 3.
MHA828
handbook, full pagewidth
0 signal (dB) -10 channel(1) 2
-20 3
-30
1
-40 102 103
1 (1) Solid line: channel 1. Dashed line: channel 2. Dotted line: channel 3.
10
f (MHz)
Fig.15 Typical crosstalk: channel 2 1 and 3.
1997 Sep 04
18
Philips Semiconductors
Product specification
Advanced monitor video controller for OSD
TDA4882
MHA829
handbook, full pagewidth
0 signal (dB) -10 channel(1) 3
-20 1 -30
2
-40 102 103
1 (1) Solid line: channel 1. Dashed line: channel 2. Dotted line: channel 3.
10
f (MHz)
Fig.16 Typical crosstalk: channel 3 1 and 2.
handbook, full pagewidth
3V Vi(CL)
1.4 V
t internal pulses input clamping tr(CL) tf(CL) no clamping td(Vblank) blanking t
MHA831
1/2 td(Vblank)
no clamping t
Fig.17 Timing of pulses at CL (pin 10).
1997 Sep 04
19
Philips Semiconductors
Product specification
Advanced monitor video controller for OSD
TDA4882
handbook, full pagewidth
td (ns)
HBL pulse (V) 1.45
80 70
0.2 60 tr 50 td(Hblank) 40 30 td(4) 20 0.5(2) 20 40 60 80 100 120 140 tr,tf(3) (ns) t
MHA830
t td(Hblank)
output signal (V) 0.74(1) Vbl
td(4)
50% of Vbl
(1) (2) (3) (4)
Black level: 0.74 V. Reference black level: 0.5 V. Rise and fall times for HBL between 0.2 and 1.45 V. td is the delay at the end of brightness blanking.
Fig.18 Typical delay between HBL pulse and brightness blanking at voltage outputs.
1997 Sep 04
20
Philips Semiconductors
Product specification
Advanced monitor video controller for OSD
11 APPLICATION AND TEST INFORMATION For high frequency measurements and special application, a printed-circuit board with only a few external components is built. Figure 19 shows the application circuit and Fig.20 the layout of the double sided printed board. All components on the underside and R13, R14 and R15 on the top are SMD types. Short HF loops and minimum crosstalk between the channels as well as input and output are achieved by properly shaped ground areas star connected to the IC ground pin. The HF input signal can be fed to the subclick connectors P1, P2 and P3 by a 50 line. The line is then terminated by a 51 resistor on the board. With choice of jumper connections (J1, J2 and J3) it is possible to connect channel inputs to its input connector, to connect all channels to one input connector (white pattern) and to ground each input via the coupling capacitor. For operation without input clamping, e.g. test mode, the DC bias can be provided by VIDC (connector P21) if a short-circuit at J4, J5 and J6 is made (solder short or low-value SMD resistor). The output signal can be monitored via 50 terminated lines at the voltage outputs (subclick connectors P4, P5 and P6). With 100 in parallel to the 50 terminated line the effective load resistance at the voltage outputs is 33 . The mismatch seen from the line towards the IC has no significant effect if the line is match terminated. A peaking circuit, C15, R16 for channel 1 (C16, R17 for channel 2 and C17, R18 for channel 3), can be added for realistic loading of the voltage outputs. Black-level adjustment is made by VIOS, VFBX (external voltages at connector P21) and resistors R19, R22 and R25 for channel 1 (channel 2: R20, R23 and R26; channel 3: R21, R24 and R27). If R19 is equal to the effective load resistor at the voltage output the reference black level (Vref(bl)) is approximately: R22 V ref(bl) = VIOS - V ref(int) - ( V ref(int) - VFBX ) x ---------R25 Vref(int) is the internal reference voltage at the feedback input (typical 5.8 V). By this it is possible to adjust the reference black level and the voltage at the current outputs independently.
TDA4882
DC control for brightness, contrast and gain is provided at connectors P21 and P22. Contrast control can also be set by the potentiometer R28 (jumper J11). The series resistor R11 is necessary if fast OSD switching is activated via 50 line (P10), a line termination can be provided at the connector P9. Clamping and blanking pulses are fed to the IC via connectors P7 and P8. Connector P23 is used for power supply. The capacitors C7 and C8 should be located as near as possible to the IC pins. 11.1 Recommendations for building the application board
* General - Double-sided board - Short HF loops by large ground plane on the rear. * Voltage outputs - Capacitive loads as small as possible - Short interconnection via resistor to ground. * Supply voltage - Capacitors as near as possible to the pins - Use of high-frequency capacitors (low self inductance, e.g. SMD). * Resonance suppression. The external interconnection inductance to the current outputs can build a resonance together with the internal substrate capacitance. A damping resistor of 10 to 30 near to the IC pin can suppress such oscillations.
1997 Sep 04
21
Philips Semiconductors
Product specification
Advanced monitor video controller for OSD
TDA4882
subclick handbook, full pagewidth connector (50 ) solder point for short-circuiting or SMD 0 resistor BC/GC2 jumper connector P21 C30 220 F (25 V) R7 C4 100 nF 110 IC1 BC/GC2 C5 22 nF Vi(b-w) P1 R1 51 J1 C1 22 nF J4 R4 5.1 k GC1 C12 22 nF C6 22 nF 3 18 1 20 IOUT1 R19 33 C21 22 nF C24 100 nF C29 2.2 F C28 100 nF C27 22 nF GND (sense)
GC1
VIDC
VFBX
VIOS
(multi-layer)
VIN1
VOUT1 2 19 C15 47 pF FB1 R13 100
P4 R22 3 k R25 9.1 k C18 22 nF
R16 33
GND
4
17
IOUT2
R20 33 C22 22 nF C25 100 nF
Vi(b-w) P2
J2
C2 22 nF J5 R5 5.1 k C13 22 nF
VIN2
VOUT2 5 16 C16 47 pF FB2 R14 100
P5 R23 3 k R26 9.1 k C19 22 nF
R2 51
TDA4882
CC 6 15
R17 33
VP C8 100 nF C7 1 nF VIN3 J6 R3 51 R6 5.1 k C14 22 nF
7
14
IOUT3
R21 33 C23 22 nF C26 100 nF
Vi(b-w) P3
J3
C3 22 nF
VOUT3 8 13 C17 47 pF R15 100
P6 R24 3 k R27 9.1 k C20 22 nF P22
R18 33
HBL
9
12
FB3
CL
GC3 10 11 C11 22 nF
GC3
CC C10 100 nF R8 1 k P7 P23 HBL P8 CL GND (power) VP P9 OSD P10
MHA832
R9 1 k
L1 100 H
R10 1 k
C31 10 F
C9 100 nF
R12 R11 1 k J10 J11 1 k R28 10 k VP (sense)
GND (sense)
Fig.19 Application circuit for test PCB.
1997 Sep 04
22
Philips Semiconductors
Product specification
Advanced monitor video controller for OSD
TDA4882
handbook, full pagewidth
C30
C29
P22 J11 J10 R28
P4
P5
P6 P10
R13
R14
R15 C31 P9 L1
IC1 R7 P21 J1 J2 J3
P23
P8
P7 P1 P2 P3
R1
R2
R3
R8
R4 C12 C1 J4 C5 R22 C4 C6 C2
R5 C14 R6 C3 C13 J5 C8 R23 J6 C7 R24 R9 C9 C11 C17 R18 R27 R11 R12 R10
R19 C15 R25 R20 C16 R26 R21 R16 C21 C24 C18 C22 C25 C19 R17 C23 C26
C20
C28
C27 C10
MHA833
Fig.20 Double sided test PCB layout.
1997 Sep 04
23
Philips Semiconductors
Product specification
Advanced monitor video controller for OSD
12 INTERNAL PIN CONFIGURATION
TDA4882
handbook, full pagewidth
20
19 CL
18
17
16 CL
15
14
13 CL
12
11
TDA4882
CL CL CL
+
1 2 3 4 5 6 7 8 9
MED911
10
+
pin pin
diode protection on all pins except pins 4 and 7
zener diode protection at pin 7
Fig.21 Internal pin configuration.
1997 Sep 04
24
Philips Semiconductors
Product specification
Advanced monitor video controller for OSD
13 PACKAGE OUTLINE DIP20: plastic dual in-line package; 20 leads (300 mil)
TDA4882
SOT146-1
D seating plane
ME
A2
A
L
A1
c Z e b1 b 20 11 MH wM (e 1)
pin 1 index E
1
10
0
5 scale
10 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 4.2 0.17 A1 min. 0.51 0.020 A2 max. 3.2 0.13 b 1.73 1.30 0.068 0.051 b1 0.53 0.38 0.021 0.015 c 0.36 0.23 0.014 0.009 D
(1)
E
(1)
e 2.54 0.10
e1 7.62 0.30
L 3.60 3.05 0.14 0.12
ME 8.25 7.80 0.32 0.31
MH 10.0 8.3 0.39 0.33
w 0.254 0.01
Z (1) max. 2.0 0.078
26.92 26.54 1.060 1.045
6.40 6.22 0.25 0.24
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT146-1 REFERENCES IEC JEDEC EIAJ SC603 EUROPEAN PROJECTION
ISSUE DATE 92-11-17 95-05-24
1997 Sep 04
25
Philips Semiconductors
Product specification
Advanced monitor video controller for OSD
14 SOLDERING 14.1 Introduction
TDA4882
There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "IC Package Databook" (order code 9398 652 90011). 14.2 Soldering by dipping or by wave
The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (Tstg max). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. 14.3 Repairing soldered joints
Apply a low voltage soldering iron (less than 24 V) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400 C, contact may be up to 5 seconds.
The maximum permissible temperature of the solder is 260 C; solder at this temperature must not be in contact with the joint for more than 5 seconds. The total contact time of successive solder waves must not exceed 5 seconds. 15 DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. 16 LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
1997 Sep 04
26
Philips Semiconductors
Product specification
Advanced monitor video controller for OSD
NOTES
TDA4882
1997 Sep 04
27
Philips Semiconductors - a worldwide company
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For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 1997
Internet: http://www.semiconductors.philips.com
SCA55
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
547047/1200/02/pp28
Date of release: 1997 Sep 04
Document order number:
9397 750 02268

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